BY BARBARA TUCK

Designers who build multimillion-gate ASIC/ SoC designs running at 300 MHz and higher need to raise the level of abstraction at which they design. An automatic pipe line- creation capability that's now shipping for Get2Chip's (San Jose, CA) architectural-level synthesis tool should boost design productivity for Verilog users and may bring them closer to the use of Superlog or C. Indeed, the C/C++ design platform is packing more punch since Forte Design Systems (San Jose, CA) recently merged its CynLib C++ with the SystemC system-level language. The acquisition by Synopsys (Mountain View, CA) of C Level Design's technology assets has also helped put an end to the fragmentation of the C language. And to extend high-level system support to programmable logic devices, Forte has cooperated with Synplicity (Sunnyvale, CA) to put together a C++ flow. Designers building a system-on-a-programmable-chip (SoPC) design with Altera's (San Jose, CA) Excalibur silicon can take ad vantage of this flow.

Get2Chip's new Pipeline Master automatically synthesizes an optimized pipelined design from a pipelined or unpipelined architectural Verilog description. An add-on to Get2Chip's VOLARE architectural synthesis tool, Pipeline Master involves interaction among dimensions in the design space, including performance, area, power, test, verification, and process rules.

Pipeline Master replaces the practice of manually coding at the register transfer level (RTL) and recoding for each tradeoff to be analyzed by exploring different pipe line alternatives with the change of a few controls/parameters. The tool transforms the number of stages in the pipeline-or datapath-and assigns operations or logic to each stage.

Pipeline Master is said to have the first design-for-test capability at an architectural level. In fact, it's said to be the first general-purpose automatic pipeline-creation tool. Adelante Technologies (Leuven, Belgium) has tools based on the Cathedral compiler technology out of IMEC, also in Leuven, which offers pipelining capability for DSP applications.

The HDL window in this Pipeline Master screenshot shows that a "for" loop labeled "twl" as a code fragment of an architectural Verilog process in an "always" block cannot be handled by conventional RTL synthesis. The Dfg window in this screenshot depicts the data flow graph of that loop after high-level synthesis. The synthesis implemented a multistage pipeline, inserting banks of registers indicated by rectangles in between stages. The Cfg window represents the control flow graph of the code, and the schematic window portrays the block diagram of the code. The critical path is the wire highlighted in red in the top section of the window.

Pipeline Master users might want to use Superlog, a high-level version of Verilog from Co-Design Automation (Los Altos, CA), for an incremental path to a higher level of abstraction. For designers who might want to use C, Get 2Chip is working with CoWare (Santa Clara, CA), which has a bus-cycle-accurate flavor of C that can be mapped to architectural Verilog.

CoWare was just honored by Synopsys, the biggest backer of SystemC, for its contribution to the Open SystemC Initiative (OSCI). CoWare executed and delivered source code to the Open System C modeling platform and built system-level products around the standard. Further unifying the C market, Synopsys has acquired the technology of C Level Design.

Synopsys has acquired the technology behind C Level's System Compiler software for RTL to C synthesis as well as a patent for synthesizing high- level languages into HDL. Synopsys is integrating C Level's CycleC simulation technology into its VCS simulator to accelerate HDL simulation.

When Forte Design Systems recently joined the OSCI and introduced the Extended SystemC (ESC) library that merges its own Cynlib C++ class library with SystemC, it pretty much closed the language wars among C variants. ESC will be offered to the SystemC community as an enhancement to the current SystemC implementation. With ESC, system, design, software, and verification, engineers can mo del and verify designs at a higher level of abstraction. This high-level modeling can be used to rapidly produce executable specifications.

In the meantime, Synplicity and For te have jointly developed a design and verification path from C++ to programmable logic devices, and Altera is working with both companies to optimize this C++ flow for its SoPC designs. This new C++ to PLD design flow advances the opportunity offered by Altera's high-end solutions that enable designers to implement sections of a design as either software or hardware. An engineer can now enter a design specified in Forte's Cynlib C++ directly into Synplicity's Synplify Pro software to obtain a gate-level netlist.

The Synplify Pro software will interface with Forte's Cynthesizer to transform the C++ code into intermediate HDL code and then an optimized gate-level netlist for the target programmable logic device.

As we head toward SoCs with tens of millions of gates, any progress in designing and verifying at a higher level of abstraction is a major step forward.